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ISBN: 1402032072

Autor:Larsson, Erik. Indem Sie ein gut erhaltenes Buch aus zweiter Hand kaufen, unterstützen Sie eine fortlaufende Wiederverwendung sowie die Verbreitung der Liebe zum Buch durch erneutes… Altro …

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(ISBN-13: 9781402032073, 978-1402032073. SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. The book is divided int… Altro …

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2005

ISBN: 9781402032073

Springer, Hardcover, Auflage: 2005, 408 Seiten, Publiziert: 2005-11-07T00:00:01Z, Produktgruppe: Book, 1.66 kg, Civil & Environmental, Engineering & Transportation, Subjects, Books, Desig… Altro …

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Introduction to Advanced System-on-Chip Test Design and Optimization. - copertina rigida, flessible

2005, ISBN: 1402032072

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Introduction to Advanced System-on-Chip Test Design and Optimization - copertina rigida, flessible

2005, ISBN: 1402032072

2005 Gebundene Ausgabe Konstruktion, Entwurf, Elektrotechnik, Elektronik, Schaltkreise und Komponenten (Bauteile), boundaryscan; SOCtestdesign; Transistor; automation; consumption; inte… Altro …

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Introduction to Advanced System-on-Chip Test Design and Optimization (Frontiers in Electronic Testing, 29)
Autore:
Titolo:
ISBN:

1402032072


SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process. TOC:Part I. Testing Concepts. Introduction. Design Flow. Design for Test. Boundary Scan.- Part II. SoC Design for Testability. System Modeling. Test Conflicts. Test Power Dissipation. Test Access Mechanism. Test Scheduling.- Part III. SoC Test Applications. A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling. An Integrated Framework for the Design and Optimization of SoC Test Solutions. Efficient Test Solutions for Core-Based Designs. Integrating Core Selection in the System-On-Chip Test Solution Design-Flow. Defect-Aware Test Scheduling. An Integrated Technique for Test Vector Selection and Test Scheduling Under Ate Memory Depth Constraint.- Appendix 1. Benchmarks.- References.- Index.

Informazioni dettagliate del libro - Introduction to Advanced System-on-Chip Test Design and Optimization (Frontiers in Electronic Testing, 29)


EAN (ISBN-13): 9781402032073
ISBN (ISBN-10): 1402032072
Copertina rigida
Anno di pubblicazione: 2005
Editore: Springer
388 Pagine
Peso: 1,093 kg
Lingua: eng/Englisch

Libro nella banca dati dal 2007-07-11T13:25:27+02:00 (Zurich)
Pagina di dettaglio ultima modifica in 2023-10-06T23:37:03+02:00 (Zurich)
ISBN/EAN: 1402032072

ISBN - Stili di scrittura alternativi:
1-4020-3207-2, 978-1-4020-3207-3
Stili di scrittura alternativi e concetti di ricerca simili:
Autore del libro : larsson
Titolo del libro: system modelling and optimization, design systems chip, design sweden, introduction advanced system chip test design and optimization, opti, little design possible, looking design, best test design

Dati dell'editore

Autore: Erik Larsson
Titolo: Frontiers in Electronic Testing; Introduction to Advanced System-on-Chip Test Design and Optimization
Editore: Springer; Springer US
388 Pagine
Anno di pubblicazione: 2005-11-07
New York; NY; US
Lingua: Inglese
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
Available
XX, 388 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Boundary Scan; SOC test design; System-on-Chip; Transistor; automation; consumption; integrated circuit; Electronic Circuits and Systems; Electrical and Electronic Engineering; Electronics and Microelectronics, Instrumentation; Engineering Design; Optical Materials; Elektrotechnik; Elektronik; Konstruktion, Entwurf; Technische Anwendung von elektronischen, magnetischen, optischen Materialien; BC

Testing Concepts.- Design Flow.- Design for Test.- Boundary Scan.- SOC Design for Testability.- System Modeling.- Test Conflicts.- Test Power Dissipation.- Test Access Mechanism.- Test Scheduling.- SOC Test Applications.- A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.- An Integrated Framework for the Design and Optimization of SOC Test Solutions.- Efficient Test Solutions for Core-Based Designs.- Core Selection in the SOC Test Design-Flow.- Defect-Aware Test Scheduling.- An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint.
System perspective to SOC test design. Overview of test problems and their modeling Test scheduling overview, extensive reference list Applicable for Master students and PhD-students working in the test field. Could also be good for researchers and professors who would like to get into the area of SOC testing, also for persons in the field who want some references Includes supplementary material: sn.pub/extras
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