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High Performance Embedded Architectures and Compilers Fourth International Conference, HiPEAC 2009 Volume editor Andre Seznec published on February, 2009 - edizione con copertina flessibile
2009, ISBN: 3540929894
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Seznec, André|Emer, Joel|O\\'Boyle, Michael|Martonosi, Margaret|Ungerer, Theo:
High Performance Embedded Architectures and Compilers - edizione con copertina flessibile2009, ISBN: 3540929894
[EAN: 9783540929895], Neubuch, [PU: Springer Berlin Heidelberg], EMBEDDED SYSTEM MIKROCONTROLLER ADA CLUSTER H.264 MULTITHREADING PROCESSING SCHEDULING SCHEME CODECOMPRESSION EXASCALECOMP… Altro …
High Performance Embedded Architectures and Compilers Fourth International Conference, HiPEAC 2009 - nuovo libro
2009
ISBN: 3540929894
2009 Kartoniert / Broschiert Embedded System, Mikrocontroller, Computerhardware, Systemanalyse und -design, Rechnerarchitektur und Logik-Entwurf, Ada; cluster; H.264; Multithreading; Pr… Altro …
High Performance Embedded Architectures and Compilers Fourth International Conference, HiPEAC 2009 Volume editor Andre Seznec published on February, 2009 - edizione con copertina flessibile
2009, ISBN: 3540929894
[EAN: 9783540929895], Neubuch, [PU: Springer], New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000., Books
High Performance Embedded Architectures and Compilers: Fourth International Conference, Hipeac 2009, Paphos, Cyprus, January 25-28, 2009 Proceedings - edizione con copertina flessibile
2009, ISBN: 9783540929895
Trade paperback, New, US edition. Satisfaction guaranteed! !, [PU: Springer]
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Informazioni dettagliate del libro - High Performance Embedded Architectures and Compilers: Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 2009, Procceding ... Science and General Issues, 5409, Band 5409)
EAN (ISBN-13): 9783540929895
ISBN (ISBN-10): 3540929894
Copertina rigida
Copertina flessibile
Anno di pubblicazione: 2009
Editore: Seznec, Andre, Springer
420 Pagine
Peso: 0,650 kg
Lingua: eng/Englisch
Libro nella banca dati dal 2009-02-20T01:12:41+01:00 (Zurich)
Pagina di dettaglio ultima modifica in 2023-09-30T13:17:49+02:00 (Zurich)
ISBN/EAN: 3540929894
ISBN - Stili di scrittura alternativi:
3-540-92989-4, 978-3-540-92989-5
Stili di scrittura alternativi e concetti di ricerca simili:
Autore del libro : seznec, ungerer, michael boyle, marton, emer, michael unger, margaret boyle, joel, andré springer
Titolo del libro: high performance embedded architectures compilers, lecture notes computer science, paphos
Dati dell'editore
Autore: André Seznec; Joel Emer; Michael O'Boyle; Margaret Martonosi; Theo Ungerer
Titolo: Lecture Notes in Computer Science; Theoretical Computer Science and General Issues; High Performance Embedded Architectures and Compilers - Fourth International Conference, HiPEAC 2009
Editore: Springer; Springer Berlin
420 Pagine
Anno di pubblicazione: 2009-01-12
Berlin; Heidelberg; DE
Lingua: Inglese
53,49 € (DE)
54,99 € (AT)
59,00 CHF (CH)
Available
XIII, 420 p.
BC; Hardcover, Softcover / Informatik, EDV/Informatik; Systemanalyse und -design; Verstehen; Informatik; Ada; Cluster; H.264; Multithreading; Processing; Scheduling; Scheme; code compression; exascale computing; heterogenous architectures; hyperthreading; manycore; memory performance; mul; optimization; Computer System Implementation; Arithmetic and Logic Structures; Processor Architectures; Input/Output and Data Communications; Logic Design; Computer Communication Networks; Computerhardware; Rechnerarchitektur und Logik-Entwurf; Netzwerk-Hardware; EA
Invited Program.- Keynote: Challenges on the Road to Exascale Computing.- Keynote: Compilers in the Manycore Era.- I Dynamic Translation and Optimisation.- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering.- Predictive Runtime Code Scheduling for Heterogeneous Architectures.- Collective Optimization.- High Speed CPU Simulation Using LTU Dynamic Binary Translation.- II Low Level Scheduling.- Integrated Modulo Scheduling for Clustered VLIW Architectures.- Software Pipelining in Nested Loops with Prolog-Epilog Merging.- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables.- III Parallelism and Resource Control.- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor.- A Hardware Task Scheduler for Embedded Video Processing.- Finding Stress Patterns in Microprocessor Workloads.- IV Communication.- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications.- MPSoC Design Using Application-Specific Architecturally Visible Communication.- Communication Based Proactive Link Power Management.- V Mapping for CMPs.- Mapping and Synchronizing Streaming Applications on Cell Processors.- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors.- Accomodating Diversity in CMPs with Heterogeneous Frequencies.- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip.- VI Power.- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture.- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.- Compiler Controlled Speculationfor Power Aware ILP Extraction in Dataflow Architectures.- VII Cache Issues.- Revisiting Cache Block Superloading.- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.- In-Network Caching for Chip Multiprocessors.- VIII Parallel Embedded Applications.- Parallel LDPC Decoding on the Cell/B.E. Processor.- Parallel H.264 Decoding on an Embedded Multicore Processor.Altri libri che potrebbero essere simili a questo:
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9783540303176 High Performance Embedded Architectures and Compilers (Conte, Tom Navarro, Nacho Hwu, Wen-mei W. Valero, Mateo Ungerer, Theo)
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