On and Off-Chip Crosstalk Avoidance in VLSI Design - nuovo libro

EAN (ISBN-13): 9781441909473
ISBN (ISBN-10): 1441909478
Anno di pubblicazione: 2010
Editore: Springer-Verlag GmbH
240 Pagine
Lingua: eng/Englisch

Libro nella banca dati dal 2008-07-07T03:25:36+02:00 (Zurich)
Pagina di dettaglio ultima modifica in 2023-03-03T13:15:49+01:00 (Zurich)
ISBN/EAN: 9781441909473

ISBN - Stili di scrittura alternativi:
1-4419-0947-8, 978-1-4419-0947-3
Stili di scrittura alternativi e concetti di ricerca simili:
Autore del libro : sunil, lamer, lamé, duan, brock lameres
Titolo del libro: vlsi, chip

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Dati dell'editore

Autore: Chunjie Duan; Brock J. LaMeres
Titolo: On and Off-Chip Crosstalk Avoidance in VLSI Design
Editore: Springer; Springer US
240 Pagine
Anno di pubblicazione: 2010-01-08
New York; NY; US
Lingua: Inglese
106,99 € (DE)
110,00 € (AT)
130,00 CHF (CH)
Available
XXIV, 240 p.

EA; E107; eBook; Nonbooks, PBS / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Crosstalk Avoidance; EDA; Noise Reduction; Off-Chip Communication; On-Chip Communication; VLSI; VLSI Design; VLSI Packaging; circuit design; construction; design automation; electronic design automation; integrated circuit; model; modeling; B; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Engineering; Computer-Aided Design (CAD); BB

On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.
Presents a novel way to combine chip and package design, reducing cross-talk so that VLSI systems can be designed to operate significantly faster Provides a comprehensive set of bus cross-talk cancellation techniques, both memoryless and memory-based Offers a battery of approaches for a VLSI designer to use, depending on the amount of cross-talk their design can tolerate, and the amount of area overhead they can afford Includes supplementary material: sn.pub/extras